Datasheet Texas Instruments SN74SSTUB32866ZWLR — Datenblatt
| Hersteller | Texas Instruments |
| Serie | SN74SSTUB32866 |
| Artikelnummer | SN74SSTUB32866ZWLR |
Konfigurierbarer 25-Bit-registrierter Puffer mit Adressparitätstest 96-BGA -40 bis 85
Datenblätter
25-Bit Configurable Registered Buffer w/Address-Parity Test datasheet
PDF, 2.0 Mb, Revision: C, Datei veröffentlicht: Nov 1, 2007
Auszug aus dem Dokument
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 96 |
| Package Type | ZWL |
| Industry STD Term | BGA |
| JEDEC Code | R-PBGA-N |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | SB866 |
| Width (mm) | 5.5 |
| Length (mm) | 13.5 |
| Thickness (mm) | .89 |
| Pitch (mm) | .8 |
| Max Height (mm) | 1.3 |
| Mechanical Data | Herunterladen |
Parameter
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | N/A ps |
| Function | DDR2 Register |
| Number of Outputs | 25 |
| Operating Frequency Range(Max) | 410 MHz |
| Operating Temperature Range | -40 to 85 C |
| Output Drive | 8 mA |
| Package Group | BGA |
| Package Size: mm2:W x L | 96BGA: 74 mm2: 5.5 x 13.5(BGA) PKG |
| Rating | Catalog |
| VCC | 1.8 V |
| t(phase error) | N/A ps |
| tsk(o) | N/A ps |
Öko-Plan
| RoHS | Compliant |
Anwendungshinweise
- DDR2 Memory Interface Clocks and Registers - OverviewPDF, 308 Kb, Datei veröffentlicht: Mar 25, 2009
This application report gives an overview of the existing JEDEC DDR2 Register and PLL Buffer specifications and compliant TI devices.
Modellreihe
Serie: SN74SSTUB32866 (3)
- HPA00322ZWLR SN74SSTUB32866ZKER SN74SSTUB32866ZWLR
Herstellerklassifikation
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers