Datasheet Texas Instruments PLMK04832NKDT — Datenblatt

Product
Folder Order
Now Support &
Community Tools &
Software Technical
Documents LMK04832
SNAS752A – AUGUST 2017 – REVISED JANUARY 2018 LMK04832 Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner With Dual Loop PLLs
1 Features 3 Description The LMK04832 is the industry's highest performance
clock conditioner with JEDEC JESD204B support and
is also pin compatible with the LMK0482x family of
devices. Maximum Clock Output Frequency: 3250 MHz
Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
Ultra-Low Noise, at 2500 MHz:
– 43 fs RMS Jitter (12 kHz to 20 MHz)
– 49 fs RMS Jitter (100 Hz to 20 MHz)
– –158 dBc/Hz Noise Floor
Ultra-Low Noise, at 3200 MHz:
– 49 fs RMS Jitter (12 kHz to 20 MHz)
– 54 fs RMS Jitter (100 Hz to 100 MHz)
– –156.5 dBc/Hz Noise Floor
PLL2 …