Datasheet Texas Instruments CDCVF2505D — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CDCVF2505 |
| Artikelnummer | CDCVF2505D |
PLL Clock Driver für Synch.
Datenblätter
CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver datasheet
PDF, 1.2 Mb, Revision: G, Datei veröffentlicht: Aug 31, 2016
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Detaillierte Beschreibung
DRAM & Gen. Purp. Apps mit Spread-Spectrum-Kompatibilität, Power-Down-Modus 8-SOIC -40 bis 85
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Verpackung
| Pin | 8 |
| Package Type | D |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 75 |
| Carrier | TUBE |
| Device Marking | CKV05 |
| Width (mm) | 3.91 |
| Length (mm) | 4.9 |
| Thickness (mm) | 1.58 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 1.75 |
| Mechanical Data | Herunterladen |
Parameter
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 150 ps |
| Function | SDR |
| Number of Outputs | 4 |
| Operating Frequency Range(Max) | 200 MHz |
| Operating Frequency Range(Min) | 24 MHz |
| Operating Temperature Range | -40 to 85 C |
| Output Drive | 12 mA |
| Package Group | SOIC |
| Package Size: mm2:W x L | 8SOIC: 29 mm2: 6 x 4.9(SOIC) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 150 ps |
| tsk(o) | 150 ps |
Öko-Plan
| RoHS | Compliant |
Anwendungshinweise
- Design and Layout Guidelines for the CDCVF2505 Clock DriverPDF, 176 Kb, Datei veröffentlicht: Nov 16, 2000
This application note describes tuning techniques, line termination methods, and filter circuit for the CDCVF2505, and it provides PCB layout guidelines.
Modellreihe
Serie: CDCVF2505 (9)
Herstellerklassifikation
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers