Datasheet Microchip PL138-48 — Datenblatt
Hersteller | Microchip |
Serie | PL138-48 |
Die PL138-48-Familie ist ein leistungsstarker, kostengünstiger 1: 4-Ausgang mit differenziellem LVPECL-Fanout-Puffer
Datenblätter
PL138-48 - 2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
PDF, 618 Kb, Datei veröffentlicht: Jun 20, 2016
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Preise
Status
PL138-48OC | PL138-48OC-R | PL138-48OI | PL138-48OI-R | |
---|---|---|---|---|
Lifecycle Status | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) |
Verpackung
PL138-48OC | PL138-48OC-R | PL138-48OI | PL138-48OI-R | |
---|---|---|---|---|
N | 1 | 2 | 3 | 4 |
Package | TSSOP | TSSOP | TSSOP | TSSOP |
Pins | 20 | 20 | 20 | 20 |
Parameter
Parameters / Models | PL138-48OC | PL138-48OC-R | PL138-48OI | PL138-48OI-R |
---|---|---|---|---|
Description | 2:4 PECL buffer 50fs Typ, 100fs Max Additive Phase Jitter | 2:4 PECL buffer 50fs Typ, 100fs Max Additive Phase Jitter | 2:4 PECL buffer 50fs Typ, 100fs Max Additive Phase Jitter | 2:4 PECL buffer 50fs Typ, 100fs Max Additive Phase Jitter |
Input Mux | Yes | Yes | Yes | Yes |
Input Type | LVDS/LVPECL/LVHSTL/SSTL/HCSL | LVDS/LVPECL/LVHSTL/SSTL/HCSL | LVDS/LVPECL/LVHSTL/SSTL/HCSL | LVDS/LVPECL/LVHSTL/SSTL/HCSL |
Operating Temperature Range, °C | 0 to +70 | 0 to +70 | -40 to +85 | -40 to +85 |
Output Frequency, Max | 1 | 1 | 1 | 1 |
Output Type | LVPECL | LVPECL | LVPECL | LVPECL |
Supply Voltage, V | 2.5V, 3.3V | 2.5V, 3.3V | 2.5V, 3.3V | 2.5V, 3.3V |
Within Device Skew, Max | 25 | 25 | 25 | 25 |
Öko-Plan
PL138-48OC | PL138-48OC-R | PL138-48OI | PL138-48OI-R | |
---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant |
Modellreihe
Serie: PL138-48 (4)
Herstellerklassifikation
- Clock and Timing > Clock and Data Distribution > Fanout Buffers