DATASHEET
CD4020BMS, CD4024BMS, CD4040BMS FN3300
Rev 1.00
October 1996 CMOS Ripple-Carry BinaryCounter/Dividers Features Pinouts High Voltage Types (20V Rating) CD4020BMS
TOP VIEW Medium Speed Operation Fully Static Operation Buffered Inputs and Outputs Q12 1 16 VDD 100% Tested for Quiescent Current at 20V Q13 2 15 Q11 Standardized Symmetrical Output Characteristics Q14 3 14 Q10 Common Reset Q6 4 13 Q8 5V, 10V and 15V Parametric Ratings Q5 5 12 Q9 Maximum Input Current of 1пЃa at 18V Over Full Package-Temperature Range;
-100nA at 18V and 25oC Q7 6 11 RESET Q4 7 10 пЃ± Noise Margin (Over Full Package Temperature Range):
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications For Description Of
�B’ Series CMOS Devices” Applications Control Counters Timers Frequency Dividers Time-Delay Circuits 9 Q1 VSS 8 CD4024BMS
TOP VIEW пЃ± 1 14 VDD RESET 2 13 NC Q7 3 12 Q1 Q6 4 11 Q2 Q5 5 10 NC Q4 6 9 Q3 VSS 7 8 NC Description
NC = NO CONNECTION CD4020BMS -14 Stage
CD4024BMS -7 Stage CD4040BMS
TOP VIEW CD4040BMS -12 Stage
CD4020BMS, CD4024BMS, and CD4040BMS are ripplecarry binary counters. All counter stages are master-slave
flip-flops. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the
RESET line resets the counter to its all zeros state. Schmitt
trigger action on the input-pulse line permits unlimited rise
and fall times. All inputs and outputs are buffered.
The CD4020BMS, CD4024BMS and the CD4040BMS is
supplied in these 14 lead outline packages: …
