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  A Simple Method to Accurately Predict PLL Reference Spur Levels Due to Leakage Current &mdash AN143
  PDF, 256 Kb, Datei veröffentlicht: Dec 17, 2013
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  Application Note 143
  December 2013
  A Simple Method to Accurately Predict PLL Reference
  Spur Levels Due to Leakage Current
  Michel Azarian and Will Ezell
  Presented is a simple model that can be used to accurately
  predict the level of reference spurs due to charge pump
  and/or op amp leakage current in a PLL system. Knowing
  how to predict these levels helps pick loop parameters
  wisely during the early stages of a PLL system design.
  Quick Review of PLLs
  The phase locked loop (PLL) is a negative feedback system
  that locks the phase and frequency of a higher frequency
  device (usually a voltage controlled oscillator, VCO) whose
  phase and frequency are not very stable over temperature
  and time to a more stable and lower frequency device
  (usually a temperature compensated or oven controlled
  crystal oscillator, TCXO or OCXO). As a black box, the PLL
  can be viewed as a frequency multiplier.
  A PLL is employed when there is the need for a high
  frequency local oscillator (LO) source. Example applications are numerous and include wireless communications,
  medical devices and instrumentation.
  Figure 1 shows the building blocks of a PLL system used …

Konstruktionshinweise

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  Uncompromised Clocking Solution for 16-Bit 2.5Gsps High Performance DAC &mdash DN555
  PDF, 225 Kb, Datei veröffentlicht: Sep 6, 2016
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  Uncompromised Clocking Solution for 16-Bit 2.5Gsps
  High Performance DAC
  Design Note 555
  Clarence Mayott
  Introduction
  The LTC В®2000 16-bit 2.5Gsps DAC offers excellent
  AC performance. For many DAC applications, phase
  noise, noise spectral density (NSD), and spurious
  free dynamic range (SFDR) are critical to maximize
  the number of possible channels in a band without
  eroding the signal to noise ratio (SNR) in the band
  of interest. High speed DACs require a clean sample
  clock to achieve the best possible noise and spurious
  performance. Using the ultralow noise and spurious
  LTC6946 PLL synthesizer as a clock source for the
  LTC2000 maximizes system performance (FigureВ 1). 16-Bit High Speed DAC
  The high spectral purity and low noise of the LTC2000
  make it an excellent signal generator. FigureВ 2 highlights the excellent additive phase noise performance
  of the LTC2000 of –165dBc/Hz at 1MHz offset and
  –147dBc/Hz at 10kHz offset with a 65MHz output. For
  output frequencies up to 100MHz, the LTC2000 has
  NSD better than –166dBm/Hz and SFDR better than
  76dB. For higher output frequencies up to 1GHz, the …

Artikel

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  Integer-N Synthesizer with Integrated VCO Yields Top Notch PLL Performance in a 4mm x 5mm Package &mdash LT Journal
  PDF, 4.9 Mb, Datei veröffentlicht: Jan 20, 2012
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  design features Integer-N Synthesizer with Integrated VCO Yields Top Notch
  PLL Performance in a 4mm Г— 5mm Package
  Michel Azarian High data throughput requirements in high bandwidth communications systems
  make the phase purity of the local oscillator critical to reliable performance. One
  way to conserve space and cost in such systems is to use an IC that combines the
  PLL and the VCO without sacrificing signal quality. The LTC6946 does just that by
  integrating a world-class frequency synthesizer, a low phase noise VCO and top-shelf
  performance, allowing designers to meet stringent RF system performance goals.
  LTC6946 SAVES TIME AND SPACE In either an RF receiver or transmitter
  system, the local oscillator (LO) plays a key
  role in achieving the desired system specifications. The main goal in such systems is
  to maximize the signal-to-noise ratio (SNR)
  of the received or transmitted signal while
  limiting board space, power and cost.
  There are several factors that limit
  the SNR in an RF system, including
  the linearity and noise figure of the
  receive or transmit chain, and the
  phase noise and spurs of the LO.
  Proper component selection in the
  RF chain limits the linearity and noise
  figure degradation to a tolerable level.
  Similarly, careful design decisions must …

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• Timing > PLL Synthesizers & VCOs > Integer-N PLLs | PLL With Integrated VCOs