Datasheet Linear Technology LT1331 — Datenblatt

Datenblätter

Preise

Verpackung

Parameter

Öko-Plan

Konstruktionshinweise

• Herunterladen
  Regulator Circuit Generates Both 3.3V and 5V Outputs from 3.3V or 5V to Run Computers and RS232 &mdash DN71
  PDF, 89 Kb, Datei veröffentlicht: Jun 1, 1993
  Auszug aus dem Dokument

  advertisement Regulator Circuit Generates Both 3.3V and 5V Outputs from
  3.3V or 5V to Run Computers and RS232 – Design Note 71
  David Dinsmore and Richard Markell
  Many portable microprocessor-based systems use a
  mix of 3.3V and 5V circuits. Some are still using only
  5V and inevitably some systems will end up being
  solely 3.3V based. If accessories are to be plugged
  into, or connected to any of these systems, a voltage
  conversion/power generation problem presents itself.
  The circuit shown in Figure 1 addresses the situation
  where either 5V or 3.3V power is available from the
  bus, but the accessory needs both 5V and 3.3V power. above the supply voltage and efficiently turns on and
  off the appropriate MOSFETs.
  IC2 also forms a flying capacitor buck/boost DC/DC
  converter circuit. This topology is used so that no
  transformers are necessary. Q1 is used to control this
  section’s voltage (V1). When VIN is at 5V, Q1 is off, forcing this section to operate as a step-down converter.
  It produces 3.3V which is sent to the 3.3V output of
  the circuit through IC4B. In this state, 5V power is sent
  directly through IC3A while IC3B and IC4A are off. The circuit consists of two sections, one being a DC/DC
  converter and the other being a pair of dual N-channel
  MOSFETs and their associated high side drivers that
  effectively form a DPDT switch. When VIN is at 3.3V, IC1 turns on Q1 shorting out the …

• Herunterladen
  RS232 Interface Circuits for 3.3V Systems &mdash DN75
  PDF, 105 Kb, Datei veröffentlicht: Oct 1, 1993
  Auszug aus dem Dokument

  RS232 Interface Circuits for 3.3V Systems – Design Note 75 Gary Maulding
  The rapid, widespread use of 3.3V logic circuits complicates the selection of RS232 interface circuits. The
  optimum choice of an interface circuit should be based
  upon several application dependent factors:
  1) Logic circuitry connected to interface chip port mouse. The LTВ®1342, LT1330, and LT1331 are all
  good RS232 transceiver choices for systems with both
  5V and 3V power. Typical performance waveforms for
  the LT1342 operating with VCC = 5V and VL = 3.3V are
  shown in Figure 2. 2) Power supply voltages available
  RECEIVER
  OUTPUT 3) Power consumption constraints
  4) Serial interface environment
  5) Mouse driving requirements
  As Figure 1 illustrates, 5V interface circuits cannot be
  used to directly connect to 3.3V CMOS logic circuits.
  The receiver output level will forward bias the logic
  circuit’s input protection diode, causing large current
  flow. In the worst case the CMOS logic circuit may
  latch up. Resistor voltage dividers or level shift buffers may be used to prevent forward biasing the CMOS
  input diode, but an RS232 transceiver designed for 3V
  logic application prevents this problem without extra
  components or power dissipation.
  Many of today’s systems have both 5V and 3V power …

• Herunterladen
  ESD Testing for RS232 Interface Circuits &mdash DN80
  PDF, 85 Kb, Datei veröffentlicht: Mar 1, 1994
  Auszug aus dem Dokument

  ESD Testing for RS232 Interface Circuits – Design Note 80
  Gary Maulding
  In 1992 Linear Technology introduced the п¬Ѓrst RS232
  interface circuits capable of surviving in excess of В±10kV
  ESD transients. Since that time, LTC has introduced
  more than 30 products with this level of protection.
  The inherent ruggedness of these products eliminates
  the need to use external protection devices in most
  applications. Not one unit has been returned from the
  п¬Ѓeld to Linear Technology for an ESD related failure
  analysis since the enhanced ESD protected devices
  were introduced.
  The В±10kV ESD voltage rating is based on the Human
  Body ESD Model. When evaluated with other standard
  ESD test methods, the superior ESD ruggedness of
  LTC’s transceivers gives equally impressive results
  when compared to older conventional designs.
  The various ESD test methodologies all share a common configuration as shown in Figure 1. A source
  capacitor is п¬Ѓrst charged to a high voltage, then the
  high voltage power supply is disconnected from the
  capacitor, and the capacitor is connected to the device
  under test through a limiting resistor. The value of the
  test capacitor and the limiting resistor differ among the …

Modellreihe

Herstellerklassifikation

• Interface > RS232/RS562 Transceivers