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  Interfacing to High Performance Pipeline ADCs &mdash DN1031
  PDF, 649 Kb, Datei veröffentlicht: Jun 21, 2013
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  Interfacing to High Performance Pipeline ADCs
  Design Note 1031
  Tyler Hutchison and Clarence Mayott Introduction
  High speed ADCs use a sample and hold input structure comprising a fast CMOS switch and a sampling
  capacitor. When the CMOS switch closes, the sampling
  capacitor shares its stored charge with the preceding
  drive circuitry (charge kickback). As the sampling
  capacitor and its stored charge increase in size, more
  attention must be paid to the drive circuitry.
  Pipeline ADCs typically have a few picofarads of
  sample capacitance. In contrast, the high performance
  16-bit 20Msps LTC В®2270 high speed ADC uses a 17pF
  sampling capacitor. The advantage of a relatively large
  sampling capacitor is a significant reduction of internal
  kT/C noise and therefore better signal-to-noise ratio
  (SNR). The disadvantage is that the part becomes more
  difficult to drive. Every time the CMOS switch closes,
  the sampling capacitor kicks back significantly more
  charge to the driver than would a smaller sampling
  capacitor.
  The interface filter, between the driver and ADC,
  demands extra attention. An inappropriate filter de-R14
  35.7О© L5 …

Artikel

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  Near Noiseless ADC Drivers for Imaging &mdash LT Journal
  PDF, 4.7 Mb, Datei veröffentlicht: Jul 9, 2013
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  design ideas Near Noiseless ADC Drivers for Imaging
  Derek Redmayne CCDs (charge coupled devices) and other sensors place heavy demands on digitizers,
  both in terms of sample rates, and in signal-to-noise ratio. The sensor output is typically
  a ground-referenced series of analog levels (pixels), possibly with transients occurring
  between the pixel boundaries. As the number of pixels increases, so does the sample
  rate of the ADC required to capture the image, with 20Msps pipelined ADCs sufficient for
  most high dynamic range applications. To ensure the highest SNR performance of the
  sampled signal, the drive circuitry for the ADC must provide low impedance, fast settling
  without introducing wideband noise and yet present high input impedance to the sensor.
  This article presents an interface circuit
  between the sensor and a high performance ADC that does not compromise
  the SNR performance. The LTC2270
  16-bit pipelined ADC family is intended
  for high end imaging applications. The
  84.1dB SNR of this family makes it attractive for imaging, but it also features
  very good SFDR—over 100dB. The input
  range is 2.1VP–P, significantly less than
  the output of most imaging devices, so
  attenuation and level-shifting is required.
  The inputs of these ADCs must be driven
  with a well-balanced differential drive. The
  single ended drive normally available from
  the sensor would force the internal virtual …

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• Data Conversion > Analog-to-Digital Converters (ADC) > High Speed ADCs (Fs >=10Msps)