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  Understanding the Effect of Clock Jitter on High Speed ADCs &mdash DN1013
  PDF, 115 Kb, Datei veröffentlicht: Aug 28, 2007
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  advertisement Understanding the Effect of Clock Jitter on High Speed ADCs
  Design Note 1013
  Derek Redmayne (LTC Applications Engineer), Eric Trelewicz (LTC Applications
  Manager) and Alison Smith (High Speed ADC Product Marketing Engineer)
  Digitizing high speed signals to a high resolution requires
  careful selection of a clock that will not compromise the
  sampling performance of the Analog to Digital Converter
  (ADC). In this article we hope to give the reader a better understanding of clock jitter and how it affects the
  performance of the high speed ADC.
  As an example we will highlight the latest high performance ADC from Linear Technology, the 16-bit, 160Msps
  LTC2209. This ADC exhibits a signal to noise ratio (SNR)
  of 77.4dB, with 100dB SFDR throughout much of the
  baseband region. Like most high speed ADCs on the
  market today, the LTC2209 uses a sample-and-hold (S&H)
  circuit that essentially takes a snapshot of the ADC input
  at an instant in time. When the S&H switch is closed,
  the network at the input of the ADC is connected to the
  sample capacitor. At the instant the switch is opened
  one half clock cycle later, the voltage on the capacitor
  is recorded and held. Variation in the time at which the
  switch is opened is known as aperture uncertainty, or jitter, and will result in an error voltage that is proportional
  to the magnitude of the jitter and the input signal slew
  rate. In other words, the greater the input frequency and …

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• Data Conversion > Analog-to-Digital Converters (ADC) > High Speed ADCs (Fs >=10Msps)

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LTC2209CUPPBF, LTC2209CUP PBF