Datasheet Texas Instruments SN74LVTH541 — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH541
Datasheet Texas Instruments SN74LVTH541

3,3-V-ABT-Oktalpuffer / Treiber mit 3-Zustands-Ausgängen

Datenblätter

SN54LVTH541, SN74LVTH541 datasheet
PDF, 1.2 Mb, Revision: G, Datei veröffentlicht: Oct 10, 2003
Auszug aus dem Dokument

Preise

Status

SN74LVTH541DBLESN74LVTH541DBRSN74LVTH541DWSN74LVTH541DWE4SN74LVTH541DWG4SN74LVTH541DWRSN74LVTH541DWRE4SN74LVTH541NSRSN74LVTH541PWSN74LVTH541PWLESN74LVTH541PWRSN74LVTH541PWRG4
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNoNoNo

Verpackung

SN74LVTH541DBLESN74LVTH541DBRSN74LVTH541DWSN74LVTH541DWE4SN74LVTH541DWG4SN74LVTH541DWRSN74LVTH541DWRE4SN74LVTH541NSRSN74LVTH541PWSN74LVTH541PWLESN74LVTH541PWRSN74LVTH541PWRG4
N123456789101112
Pin202020202020202020202020
Package TypeDBDBDWDWDWDWDWNSPWPWPWPW
Industry STD TermSSOPSSOPSOICSOICSOICSOICSOICSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.37.57.57.57.57.55.34.44.44.44.4
Length (mm)7.27.212.812.812.812.812.812.66.56.56.56.5
Thickness (mm)1.951.952.352.352.352.352.351.951111
Pitch (mm).65.651.271.271.271.271.271.27.65.65.65.65
Max Height (mm)222.652.652.652.652.6521.21.21.21.2
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen
Package QTY20002525252000200020007020002000
CarrierLARGE T&RTUBETUBETUBELARGE T&RLARGE T&RLARGE T&RTUBELARGE T&RLARGE T&R
Device MarkingLXH541LVTH541LVTH541LVTH541LVTH541LVTH541LVTH541LXH541LXH541LXH541

Parameter

Parameters / ModelsSN74LVTH541DBLE
SN74LVTH541DBLE
SN74LVTH541DBR
SN74LVTH541DBR
SN74LVTH541DW
SN74LVTH541DW
SN74LVTH541DWE4
SN74LVTH541DWE4
SN74LVTH541DWG4
SN74LVTH541DWG4
SN74LVTH541DWR
SN74LVTH541DWR
SN74LVTH541DWRE4
SN74LVTH541DWRE4
SN74LVTH541NSR
SN74LVTH541NSR
SN74LVTH541PW
SN74LVTH541PW
SN74LVTH541PWLE
SN74LVTH541PWLE
SN74LVTH541PWR
SN74LVTH541PWR
SN74LVTH541PWRG4
SN74LVTH541PWRG4
Approx. Price (US$)0.65 | 1ku0.65 | 1ku
Bits8888888888
Bits(#)88
F @ Nom Voltage(Max), Mhz160160160160160160160160160160
F @ Nom Voltage(Max)(Mhz)160160
ICC @ Nom Voltage(Max), mA0.0050.0050.0050.0050.0050.0050.0050.0050.0050.005
ICC @ Nom Voltage(Max)(mA)0.0050.005
Input TypeTTL/CMOSTTL/CMOS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64
Output Drive (IOL/IOH)(Max)(mA)-32/64-32/64
Output TypeLVTTLLVTTL
Package GroupSSOPSSOPSOICSOICSOICSOICSOICSOTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SO: 98 mm2: 7.8 x 12.6(SO)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Package Size: mm2:W x L (PKG)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.63.63.6
VCC(Max)(V)3.63.6
VCC(Min), V2.72.72.72.72.72.72.72.72.72.7
VCC(Min)(V)2.72.7
Voltage(Nom), V3.33.33.33.33.33.33.33.33.33.3
Voltage(Nom)(V)3.33.3
tpd @ Nom Voltage(Max), ns3.53.53.53.53.53.53.53.53.53.5
tpd @ Nom Voltage(Max)(ns)3.53.5

Öko-Plan

SN74LVTH541DBLESN74LVTH541DBRSN74LVTH541DWSN74LVTH541DWE4SN74LVTH541DWG4SN74LVTH541DWRSN74LVTH541DWRE4SN74LVTH541NSRSN74LVTH541PWSN74LVTH541PWLESN74LVTH541PWRSN74LVTH541PWRG4
RoHSNot CompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantNot CompliantCompliantCompliant
Pb FreeNoNo

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver