Datasheet Texas Instruments SN74LVTH162541 — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH162541
Datasheet Texas Instruments SN74LVTH162541

3,3-V-ABT-16-Bit-Puffer / -Treiber mit 3-Zustands-Ausgängen

Datenblätter

SN54LVTH162541, SN74LVTH162541 datasheet
PDF, 313 Kb, Revision: F, Datei veröffentlicht: Nov 1, 2006
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Preise

Status

SN74LVTH162541DGGRSN74LVTH162541DLSN74LVTH162541DLR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

Verpackung

SN74LVTH162541DGGRSN74LVTH162541DLSN74LVTH162541DLR
N123
Pin484848
Package TypeDGGDLDL
Industry STD TermTSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY2000251000
CarrierLARGE T&RTUBELARGE T&R
Device MarkingLVTH162541LVTH162541LVTH162541
Width (mm)6.17.497.49
Length (mm)12.515.8815.88
Thickness (mm)1.152.592.59
Pitch (mm).5.635.635
Max Height (mm)1.22.792.79
Mechanical DataHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsSN74LVTH162541DGGR
SN74LVTH162541DGGR
SN74LVTH162541DL
SN74LVTH162541DL
SN74LVTH162541DLR
SN74LVTH162541DLR
Bits161616
F @ Nom Voltage(Max), Mhz160160160
ICC @ Nom Voltage(Max), mA0.0050.0050.005
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-12/12-12/12-12/12
Package GroupTSSOPSSOPSSOP
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)
RatingCatalogCatalogCatalog
Schmitt TriggerNoNoNo
Technology FamilyLVTLVTLVT
VCC(Max), V3.63.63.6
VCC(Min), V2.72.72.7
Voltage(Nom), V3.33.33.3
tpd @ Nom Voltage(Max), ns4.14.14.1

Öko-Plan

SN74LVTH162541DGGRSN74LVTH162541DLSN74LVTH162541DLR
RoHSCompliantCompliantCompliant

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver