Datasheet Texas Instruments SN74LVT8996-EP — Datenblatt
| Hersteller | Texas Instruments |
| Serie | SN74LVT8996-EP |
Verbessertes Produkt 3,3-V Abt 10-Bit Multidrop-adressierbarer Ieee Std 1149.1 Abgriff-Transceiver
Datenblätter
SN74LVT8996-EP datasheet
PDF, 758 Kb, Datei veröffentlicht: Sep 3, 2003
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Status
| SN74LVT8996IPWREP | V62/04644-01YE | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No |
Verpackung
| SN74LVT8996IPWREP | V62/04644-01YE | |
|---|---|---|
| N | 1 | 2 |
| Pin | 24 | 24 |
| Package Type | PW | PW |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 2000 | 2000 |
| Carrier | LARGE T&R | LARGE T&R |
| Device Marking | LT8996EP | LT8996EP |
| Width (mm) | 4.4 | 4.4 |
| Length (mm) | 7.8 | 7.8 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Herunterladen | Herunterladen |
Parameter
| Parameters / Models | SN74LVT8996IPWREP | V62/04644-01YE |
|---|---|---|
| Bits | 10 | 10 |
| ICC @ Nom Voltage(Max), mA | 20 | 20 |
| Input Type | TTL/CMOS | TTL/CMOS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Output Drive (IOL/IOH)(Max), mA | 64/-32 | 64/-32 |
| Output Type | LVTTL | LVTTL |
| Package Group | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) |
| Rating | HiRel Enhanced Product | HiRel Enhanced Product |
| Technology Family | LVT | LVT |
| VCC(Max), V | 3.6 | 3.6 |
| VCC(Min), V | 2.7 | 2.7 |
Öko-Plan
| SN74LVT8996IPWREP | V62/04644-01YE | |
|---|---|---|
| RoHS | Compliant | Compliant |
Anwendungshinweise
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Modellreihe
Serie: SN74LVT8996-EP (2)
Herstellerklassifikation
- Semiconductors> Space & High Reliability> Logic Products> Specialty Logic Products> Boundary Scan (JTAG)