Datasheet Texas Instruments SN74LVT240A — Datenblatt

HerstellerTexas Instruments
SerieSN74LVT240A
Datasheet Texas Instruments SN74LVT240A

3,3-V-ABT-Oktalpuffer / Treiber mit 3-Zustands-Ausgängen

Datenblätter

SN74LVT240A datasheet
PDF, 1.1 Mb, Revision: K, Datei veröffentlicht: Jan 14, 2004
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Preise

Status

SN74LVT240ADBRSN74LVT240ADWSN74LVT240ADWE4SN74LVT240ADWG4SN74LVT240ADWRSN74LVT240ANSRSN74LVT240APWSN74LVT240APWG4SN74LVT240APWRSN74LVT240APWRE4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNo

Verpackung

SN74LVT240ADBRSN74LVT240ADWSN74LVT240ADWE4SN74LVT240ADWG4SN74LVT240ADWRSN74LVT240ANSRSN74LVT240APWSN74LVT240APWG4SN74LVT240APWRSN74LVT240APWRE4
N12345678910
Pin20202020202020202020
Package TypeDBDWDWDWDWNSPWPWPWPW
Industry STD TermSSOPSOICSOICSOICSOICSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY200025252520002000707020002000
CarrierLARGE T&RTUBETUBETUBELARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&R
Device MarkingLX240ALVT240ALVT240ALVT240ALVT240ALVT240ALX240ALX240ALX240ALX240A
Width (mm)5.37.57.57.57.55.34.44.44.44.4
Length (mm)7.212.812.812.812.812.66.56.56.56.5
Thickness (mm)1.952.352.352.352.351.951111
Pitch (mm).651.271.271.271.271.27.65.65.65.65
Max Height (mm)22.652.652.652.6521.21.21.21.2
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsSN74LVT240ADBR
SN74LVT240ADBR
SN74LVT240ADW
SN74LVT240ADW
SN74LVT240ADWE4
SN74LVT240ADWE4
SN74LVT240ADWG4
SN74LVT240ADWG4
SN74LVT240ADWR
SN74LVT240ADWR
SN74LVT240ANSR
SN74LVT240ANSR
SN74LVT240APW
SN74LVT240APW
SN74LVT240APWG4
SN74LVT240APWG4
SN74LVT240APWR
SN74LVT240APWR
SN74LVT240APWRE4
SN74LVT240APWRE4
Bits8888888888
F @ Nom Voltage(Max), Mhz160160160160160160160160160160
ICC @ Nom Voltage(Max), mA0.0050.0050.0050.0050.0050.0050.0050.0050.0050.005
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64
Package GroupSSOPSOICSOICSOICSOICSOTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SO: 98 mm2: 7.8 x 12.6(SO)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.63.63.6
VCC(Min), V2.72.72.72.72.72.72.72.72.72.7
Voltage(Nom), V3.33.33.33.33.33.33.33.33.33.3
tpd @ Nom Voltage(Max), ns3.83.83.83.83.83.83.83.83.83.8

Öko-Plan

SN74LVT240ADBRSN74LVT240ADWSN74LVT240ADWE4SN74LVT240ADWG4SN74LVT240ADWRSN74LVT240ANSRSN74LVT240APWSN74LVT240APWG4SN74LVT240APWRSN74LVT240APWRE4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Inverting Buffer/Driver