Datasheet Texas Instruments SN74GTLPH1645 — Datenblatt

Hersteller	Texas Instruments
Serie	SN74GTLPH1645

Datenblätter

Preise

Status

Verpackung

Parameter

Parameters / Models	74GTLPH1645DGGRG4	SN74GTLPH1645DGGR	SN74GTLPH1645DGVR
Bits	16	16	16
F @ Nom Voltage(Max), Mhz	175	175	175
ICC @ Nom Voltage(Max), mA	40	40	40
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	100	100	100
Package Group	TSSOP	TSSOP	TVSOP
Package Size: mm2:W x L, PKG	56TSSOP: 113 mm2: 8.1 x 14(TSSOP)	56TSSOP: 113 mm2: 8.1 x 14(TSSOP)	56TVSOP: 72 mm2: 6.4 x 11.3(TVSOP)
Rating	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No
Technology Family	GTLP	GTLP	GTLP
VCC(Max), V	3.45	3.45	3.45
VCC(Min), V	3.15	3.15	3.15
Voltage(Nom), V	3.3	3.3	3.3
tpd @ Nom Voltage(Max), ns	9.4	9.4	9.4

Öko-Plan

Anwendungshinweise

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  PDF, 496 Kb, Datei veröffentlicht: Jan 1, 2001
  Using a question-and-answer format, advantages of TI?s GTLP devices, particularly for backplane applications, are presented, as well as differences between GTLP and GTL/LVDS devices. Applicable topics include data throughput rates, synchronous clocks, price and alternative sources, bus transceivers, live insertion, power consumption, backplane termination, voltage translation, IBIS and HSPICE mode
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  Logic in Live-Insertion Applications With a Focus on GTLP
  PDF, 493 Kb, Datei veröffentlicht: Jan 14, 2002
  Live-insertion capability is an essential part of today?s high-speed data systems because those systems are expected to run continuously without being powered down. This application report delves into the cause and prevention of live-insertion and nanosecond-discontinuity effects, using both simulation and actual test measurements from a specially built GTLP EVM. Hypothetical cases for precharge c
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  Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
  PDF, 585 Kb, Datei veröffentlicht: Apr 5, 2001
  This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines, key factors that influence the bus line delay, and the impedance of bus lines are described.The theoretical
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  Fast GTLP Backplanes With the GTLPH1655 (Rev. A)
  PDF, 1.1 Mb, Revision: A, Datei veröffentlicht: Sep 19, 2000
  This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OECE circuitry and implementation of theTexas Instruments TI-OPCE circuitry, that have been incorporated in the GTLPH1655 device. These improvements significantly improve signal integrity in distributed loads.This application report describes the physical principles of fast
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  Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
  PDF, 209 Kb, Datei veröffentlicht: May 10, 2002
  Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Modellreihe

Herstellerklassifikation

• Semiconductors> Logic> Backplane Logic (GTL/TTL/BTL/ECL Transceiver/Translator)