Datasheet Texas Instruments SN74AVC16374 — Datenblatt

HerstellerTexas Instruments
SerieSN74AVC16374
Datasheet Texas Instruments SN74AVC16374

16-Bit-kantengetriggertes D-Flip-Flop mit 3-Zustands-Ausgängen

Datenblätter

SN74AVC16374 datasheet
PDF, 854 Kb, Revision: H, Datei veröffentlicht: Feb 8, 2005
Auszug aus dem Dokument

Preise

Status

74AVC16374DGGRE4SN74AVC16374DGGRSN74AVC16374DGVRSN74AVC16374GQLRSN74AVC16374ZQLR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYesNoYesYes

Verpackung

74AVC16374DGGRE4SN74AVC16374DGGRSN74AVC16374DGVRSN74AVC16374GQLRSN74AVC16374ZQLR
N12345
Pin4848485656
Package TypeDGGDGGDGVGQLZQL
Industry STD TermTSSOPTSSOPTVSOPBGA MICROSTAR JUNIORBGA MICROSTAR JUNIOR
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PBGA-NR-PBGA-N
Package QTY2000200020001000
CarrierLARGE T&RLARGE T&RLARGE T&RLARGE T&R
Device MarkingAVC16374AVC16374CVA374CVA374
Width (mm)6.16.14.44.54.5
Length (mm)12.512.59.777
Thickness (mm)1.151.151.05.75.75
Pitch (mm).5.5.4.65.65
Max Height (mm)1.21.21.211
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / Models74AVC16374DGGRE4
74AVC16374DGGRE4
SN74AVC16374DGGR
SN74AVC16374DGGR
SN74AVC16374DGVR
SN74AVC16374DGVR
SN74AVC16374GQLR
SN74AVC16374GQLR
SN74AVC16374ZQLR
SN74AVC16374ZQLR
3-State OutputYesYesYesYesYes
Approx. Price (US$)1.88 | 1ku
Bits16161616
Bits(#)16
F @ Nom Voltage(Max), Mhz200200200200
F @ Nom Voltage(Max)(Mhz)200
ICC @ Nom Voltage(Max), mA0.040.040.040.04
ICC @ Nom Voltage(Max)(mA)0.04
Input TypeTTL
CMOS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Output Drive (IOL/IOH)(Max), mA12/-1212/-1212/-1212/-12
Output Drive (IOL/IOH)(Max)(mA)12/-12
Output TypeCMOS
Package GroupTSSOPTSSOPTVSOPBGA MICROSTAR JUNIORBGA MICROSTAR JUNIOR
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TVSOP: 62 mm2: 6.4 x 9.7(TVSOP)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
Package Size: mm2:W x L (PKG)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
RatingCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNo
Technology FamilyAVCAVCAVCAVCAVC
VCC(Max), V3.63.63.63.6
VCC(Max)(V)3.6
VCC(Min), V1.21.21.21.2
VCC(Min)(V)1.2
Voltage(Nom), V1.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.3
Voltage(Nom)(V)1.2
1.5
1.8
2.5
3.3
tpd @ Nom Voltage(Max), ns7.3,8.4,6.7,4.1,3.37.3,8.4,6.7,4.1,3.37.3,8.4,6.7,4.1,3.37.3,8.4,6.7,4.1,3.3
tpd @ Nom Voltage(Max)(ns)7.3
8.4
6.7
4.1
3.3

Öko-Plan

74AVC16374DGGRE4SN74AVC16374DGGRSN74AVC16374DGVRSN74AVC16374GQLRSN74AVC16374ZQLR
RoHSCompliantCompliantCompliantNot CompliantCompliant
Pb FreeNo

Anwendungshinweise

  • Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)
    PDF, 126 Kb, Revision: B, Datei veröffentlicht: Jul 7, 1999
    Texas Instruments (TI[TM]) next-generation logic is called the Advanced Very-low-voltage CMOS (AVC) family. The AVCfamily features TI?s Dynamic Output Control (DOC[TM]) circuit (patent pending). DOC circuitry automatically lowers the outputimpedance of the circuit at the beginning of a signal transition, providing enough current to achieve high signaling speeds, thensubsequently raises the i
  • AVC Logic Family Technology and Applications (Rev. A)
    PDF, 148 Kb, Revision: A, Datei veröffentlicht: Aug 26, 1998
    Texas Instruments (TI?) announces the industry?s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. TI?s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family features TI?s Dynamic Output Control (
  • Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)
    PDF, 390 Kb, Revision: B, Datei veröffentlicht: Apr 30, 2015
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revision: A, Datei veröffentlicht: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop