Datasheet Texas Instruments SN74ALVCH16721 — Datenblatt

HerstellerTexas Instruments
SerieSN74ALVCH16721
Datasheet Texas Instruments SN74ALVCH16721

3,3-V-20-Bit-Flip-Flop mit 3-Zustands-Ausgängen

Datenblätter

SN74ALVCH16721 datasheet
PDF, 365 Kb, Revision: E, Datei veröffentlicht: Aug 3, 2004
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Preise

Status

SN74ALVCH16721DGGRSN74ALVCH16721DLSN74ALVCH16721DLR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

Verpackung

SN74ALVCH16721DGGRSN74ALVCH16721DLSN74ALVCH16721DLR
N123
Pin565656
Package TypeDGGDLDL
Industry STD TermTSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY2000201000
CarrierLARGE T&RTUBELARGE T&R
Device MarkingALVCH16721ALVCH16721ALVCH16721
Width (mm)6.17.497.49
Length (mm)1418.4118.41
Thickness (mm)1.152.592.59
Pitch (mm).5.635.635
Max Height (mm)1.22.792.79
Mechanical DataHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsSN74ALVCH16721DGGR
SN74ALVCH16721DGGR
SN74ALVCH16721DL
SN74ALVCH16721DL
SN74ALVCH16721DLR
SN74ALVCH16721DLR
3-State OutputYesYesYes
Bits202020
F @ Nom Voltage(Max), Mhz150150150
ICC @ Nom Voltage(Max), mA0.040.040.04
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-24
Package GroupTSSOPSSOPSSOP
Package Size: mm2:W x L, PKG56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56SSOP: 191 mm2: 10.35 x 18.42(SSOP)56SSOP: 191 mm2: 10.35 x 18.42(SSOP)
RatingCatalogCatalogCatalog
Schmitt TriggerNoNoNo
Technology FamilyALVCALVCALVC
VCC(Max), V3.63.63.6
VCC(Min), V1.651.651.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns5.6,5.1,4.35.6,5.1,4.35.6,5.1,4.3

Öko-Plan

SN74ALVCH16721DGGRSN74ALVCH16721DLSN74ALVCH16721DLR
RoHSCompliantCompliantCompliant

Anwendungshinweise

  • Timing Differences of 10-pF Versus 50pF Loading
    PDF, 47 Kb, Datei veröffentlicht: Nov 1, 1996
    The 'ALVCH16244 is a 16-bit advanced low voltage CMOS (ALVC) unidirectional driver. Typically, data sheet values for tpd, ten, and tdis are characterized under a 50-pF capacitive load with a temperature range of -40?C to 85?C. At times these drivers are used in memory addressing for dual in-line memory modules (DIMM) with a 10-pF load and and temperature range of 0?C to 70?C. This document provide
  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, Datei veröffentlicht: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, Revision: A, Datei veröffentlicht: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, Revision: A, Datei veröffentlicht: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop