Datasheet Texas Instruments SN74ALVCH162827 — Datenblatt

HerstellerTexas Instruments
SerieSN74ALVCH162827
Datasheet Texas Instruments SN74ALVCH162827

20-Bit-Puffer / Treiber mit 3-Zustands-Ausgängen

Datenblätter

SN74ALVCH162827 datasheet
PDF, 339 Kb, Revision: H, Datei veröffentlicht: Aug 16, 2004
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Preise

Status

SN74ALVCH162827DGGRSN74ALVCH162827DLSN74ALVCH162827DLRSN74ALVCH162827GRSN74ALVCH162827VR
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNo

Verpackung

SN74ALVCH162827DGGRSN74ALVCH162827DLSN74ALVCH162827DLRSN74ALVCH162827GRSN74ALVCH162827VR
N12345
Pin5656565656
Package TypeDGGDLDLDGGDGV
Industry STD TermTSSOPSSOPSSOPTSSOPTVSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)6.17.497.496.14.4
Length (mm)1418.4118.411411.3
Thickness (mm)1.152.592.591.151.05
Pitch (mm).5.635.635.5.4
Max Height (mm)1.22.792.791.21.2
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen
Package QTY20100020002000
CarrierTUBELARGE T&RLARGE T&RLARGE T&R
Device MarkingALVCH162827ALVCH162827ALVCH162827VH2827

Parameter

Parameters / ModelsSN74ALVCH162827DGGR
SN74ALVCH162827DGGR
SN74ALVCH162827DL
SN74ALVCH162827DL
SN74ALVCH162827DLR
SN74ALVCH162827DLR
SN74ALVCH162827GR
SN74ALVCH162827GR
SN74ALVCH162827VR
SN74ALVCH162827VR
Approx. Price (US$)0.71 | 1ku
Bits20202020
Bits(#)20
F @ Nom Voltage(Max), Mhz100100100100
F @ Nom Voltage(Max)(Mhz)100
ICC @ Nom Voltage(Max), mA0.040.040.040.04
ICC @ Nom Voltage(Max)(mA)0.04
Input TypeLVTTL
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Output Drive (IOL/IOH)(Max), mA-12/12-12/12-12/12-12/12
Output Drive (IOL/IOH)(Max)(mA)-12/12
Output TypeLVTTL
Package GroupTSSOPSSOPSSOPTSSOPTVSOP
Package Size: mm2:W x L, PKG56SSOP: 191 mm2: 10.35 x 18.42(SSOP)56SSOP: 191 mm2: 10.35 x 18.42(SSOP)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56TVSOP: 72 mm2: 6.4 x 11.3(TVSOP)
Package Size: mm2:W x L (PKG)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNo
Technology FamilyALVCALVCALVCALVCALVC
VCC(Max), V3.63.63.63.6
VCC(Max)(V)3.6
VCC(Min), V1.651.651.651.65
VCC(Min)(V)1.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.3
Voltage(Nom)(V)1.8
2.5
2.7
3.3
tpd @ Nom Voltage(Max), ns4.4,3.84.4,3.84.4,3.84.4,3.8
tpd @ Nom Voltage(Max)(ns)4.4
3.8

Öko-Plan

SN74ALVCH162827DGGRSN74ALVCH162827DLSN74ALVCH162827DLRSN74ALVCH162827GRSN74ALVCH162827VR
RoHSNot CompliantCompliantCompliantCompliantCompliant
Pb FreeNo

Anwendungshinweise

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, Datei veröffentlicht: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, Revision: A, Datei veröffentlicht: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, Revision: A, Datei veröffentlicht: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver