Datasheet Texas Instruments SN74ALVC16821 — Datenblatt

HerstellerTexas Instruments
SerieSN74ALVC16821

3,3-V-20-Bit-Busschnittstellen-Flipflop mit 3-Zustands-Ausgängen

Datenblätter

3.3-V 20-Bit Bus-Interface Flip-Flop With 3-State Outputs (Rev. A)
PDF, 186 Kb, Revision: A, Datei veröffentlicht: Aug 1, 1995

Preise

Status

SN74ALVC16821DLSN74ALVC16821DLR
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNoNo

Verpackung

SN74ALVC16821DLSN74ALVC16821DLR
N12
Pin5656
Package TypeDLDL
Industry STD TermSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Width (mm)7.497.49
Length (mm)18.4118.41
Thickness (mm)2.592.59
Pitch (mm).635.635
Max Height (mm)2.792.79
Mechanical DataHerunterladenHerunterladen

Öko-Plan

SN74ALVC16821DLSN74ALVC16821DLR
RoHSNot CompliantNot Compliant
Pb FreeNoNo

Anwendungshinweise

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, Datei veröffentlicht: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, Revision: A, Datei veröffentlicht: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, Revision: A, Datei veröffentlicht: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

Modellreihe

Serie: SN74ALVC16821 (2)

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop