Datasheet Texas Instruments SN65LVDS104DR — Datenblatt

HerstellerTexas Instruments
SerieSN65LVDS104
ArtikelnummerSN65LVDS104DR
Datasheet Texas Instruments SN65LVDS104DR

1: 4 LVDS Clock Fanout Buffer 16-SOIC -40 bis 85

Datenblätter

SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet
PDF, 1.2 Mb, Revision: G, Datei veröffentlicht: Dec 31, 2015
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin16
Package TypeD
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY2500
CarrierLARGE T&R
Device MarkingLVDS104
Width (mm)3.91
Length (mm)9.9
Thickness (mm)1.58
Pitch (mm)1.27
Max Height (mm)1.75
Mechanical DataHerunterladen

Parameter

Input Frequency(Max)400 MHz
Input LevelLVDS
Number of Outputs4
Operating Temperature Range-40 to 85 C
Output Frequency(Max)400 MHz
Output LevelLVDS
Package GroupSOIC
Package Size: mm2:W x L16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG
RatingCatalog
VCC3.3 V
VCC Out3.3 V

Öko-Plan

RoHSCompliant

Anwendungshinweise

  • DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, Datei veröffentlicht: Feb 19, 2003
  • AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, Revision: C, Datei veröffentlicht: Oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Modellreihe

Herstellerklassifikation

  • Semiconductors > Clock and Timing > Clock Buffers > Differential