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SCANSTA101
www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master
Check for Samples: SCANSTA101 FEATURES DESCRIPTION The SCANSTA101 is designed to function as a test
master for an IEEE 1149.1 boundary scan test
system. It is suitable for use in embedded IEEE
1149.1 applications and as a component in a standalone boundary scan tester. 1 2 Compatible with IEEE Std. 1149.1 (JTAG) Test
Access Port and Boundary Scan Architecture
Supported by Texas Instruments' SCAN Ease
(SCAN Embedded Application Software
Enabler) Software Rev 2.0
Uses Generic, Asynchronous Processor
Interface; Compatible with a Wide Range of
Processors and Processor Clock (PCLK)
Frequencies
16-Bit Data Interface (IP Scalable to 32-bit)
2k x 32 Bit Dual-Port Memory
Load-on-the-Fly (LotF) and Preloaded Vector
Operating Modes Supported
On-Board Sequencer Allows Multi-Vector
Operations such as those Required to Load
Data Into an FPGA
On-Board Compares Support Test Data In
(TDI) Validation Against Preloaded Expected …
