Datasheet Texas Instruments LMK61PD0A2-SIAR — Datenblatt

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SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 LMK61PD0A2 Ultra-Low Jitter Pin Selectable Oscillator
1 Features 3 Description The LMK61PD0A2 is an ultra-low jitter PLLatinumTM
pin selectable oscillator that generates commonly
used reference clocks. The device is preprogrammed in factory to support seven unique
reference clock frequencies that can be selected by
pin-strapping each of FS[1:0] to VDD, GND or NC (no
connect). Output format is selected between
LVPECL, LVDS, or HCSL by pin-strapping OS to
VDD, GND or NC. Internal power conditioning provide
excellent power supply ripple rejection (PSRR),
reducing the cost and complexity of the power
delivery network. The device operates from a single
3.3 V В± 5% supply. 1 Ultra-low Noise, High Performance
– Jitter: 90 fs RMS typical fOUT > 100 MHz
– PSRR: -70 dBc, robust supply noise immunity
Flexible Output Frequency and Format; User
Selectable …