Datasheet Texas Instruments DS90CR286ATDGGRQ1 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | DS90CR286AT-Q1 |
| Artikelnummer | DS90CR286ATDGGRQ1 |
3,3-V-Daten-Strobe-LVDS-Empfänger mit steigender Flanke 28-Bit-Chan-Link 66 MHz 56-TSSOP -40 bis 105
Datenblätter
DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz datasheet
PDF, 2.1 Mb, Revision: A, Datei veröffentlicht: Dec 6, 2015
Auszug aus dem Dokument
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Verpackung
| Pin | 56 | 56 |
| Package Type | DGG | DGG |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 2000 | 2000 |
| Carrier | LARGE T&R | LARGE T&R |
| Device Marking | DGG | DS90CR286ATQ |
| Width (mm) | 6.1 | 6.1 |
| Length (mm) | 14 | 14 |
| Thickness (mm) | 1.15 | 1.15 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Herunterladen | Herunterladen |
Parameter
| Clock Max | 66 MHz |
| Clock Min | 20 MHz |
| Compression Ratio | 28 to 4 |
| Data Throughput | 1848 Mbps |
| ESD | 4 kV |
| Function | Deserializer |
| Input Compatibility | LVDS |
| Operating Temperature Range | -40 to 105 C |
| Output Compatibility | LVCMOS |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) PKG |
| Parallel Bus Width | 28 bits |
| Protocols | Channel-Link I |
| Rating | Automotive |
| Supply Voltage(s) | 3.3 V |
Öko-Plan
| RoHS | Compliant |
Design Kits und Evaluierungsmodule
- Evaluation Modules & Boards: FLINK3V8BT-85
Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices
Lifecycle Status: Active (Recommended for new designs)
Anwendungshinweise
- Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, Datei veröffentlicht: Jan 13, 2016
Modellreihe
Serie: DS90CR286AT-Q1 (2)
- DS90CR286ATDGGQ1 DS90CR286ATDGGRQ1
Herstellerklassifikation
- Semiconductors > Interface > LVDS/M-LVDS/PECL > SerDes/Channel-Link