Datasheet Texas Instruments CY54FCT373T — Datenblatt

HerstellerTexas Instruments
SerieCY54FCT373T
Datasheet Texas Instruments CY54FCT373T

Oktale transparente D-Latches mit 3-Zustands-Ausgängen

Datenblätter

8-Bit Latches datasheet
PDF, 678 Kb, Revision: B, Datei veröffentlicht: Aug 20, 2001
Auszug aus dem Dokument

Preise

Status

5962-9221701MRA5962-9221702MRA5962-9221703M2ACY54FCT373ATDMB
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNo

Verpackung

5962-9221701MRA5962-9221702MRA5962-9221703M2ACY54FCT373ATDMB
N1234
Pin20202020
Package TypeJJFKJ
Industry STD TermCDIPCDIPLCCCCDIP
JEDEC CodeR-GDIP-TR-GDIP-TS-CQCC-NR-GDIP-T
Package QTY1111
CarrierTUBETUBETUBETUBE
Width (mm)6.926.928.896.92
Length (mm)24.224.28.8924.2
Thickness (mm)4.574.571.834.57
Pitch (mm)2.542.541.272.54
Max Height (mm)5.085.082.035.08
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladen
Device Marking5962-9221702MR

Parameter

Parameters / Models5962-9221701MRA
5962-9221701MRA
5962-9221702MRA5962-9221703M2ACY54FCT373ATDMB
Bits8
F @ Nom Voltage(Max), Mhz70
ICC @ Nom Voltage(Max), mA0.5
Operating Temperature Range, C-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA24/-24
Package GroupCDIPCDIP
Package Size: mm2:W x L, PKGSee datasheet (CDIP)See datasheet (CDIP)
RatingMilitaryMilitary
Technology FamilyFCTFCT
tpd @ Nom Voltage(Max), ns4.2

Öko-Plan

5962-9221701MRA5962-9221702MRA5962-9221703M2ACY54FCT373ATDMB
RoHSSee ti.comSee ti.comSee ti.comSee ti.com

Anwendungshinweise

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revision: C, Datei veröffentlicht: Dec 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, Datei veröffentlicht: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revision: A, Datei veröffentlicht: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Introduction to Logic
    PDF, 93 Kb, Datei veröffentlicht: Apr 30, 2015

Modellreihe

Herstellerklassifikation

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers