Datasheet Texas Instruments CD74ACT109 — Datenblatt

HerstellerTexas Instruments
SerieCD74ACT109
Datasheet Texas Instruments CD74ACT109

Dual Positive-Edge Triggered JK Flip-Flops mit Set und Reset

Datenblätter

CD54ACT109, CD74ACT109 datasheet
PDF, 878 Kb, Datei veröffentlicht: Jan 24, 2003
Auszug aus dem Dokument

Preise

Status

CD74ACT109ECD74ACT109EE4CD74ACT109MCD74ACT109M96CD74ACT109M96E4CD74ACT109ME4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNo

Verpackung

CD74ACT109ECD74ACT109EE4CD74ACT109MCD74ACT109M96CD74ACT109M96E4CD74ACT109ME4
N123456
Pin161616161616
Package TypeNNDDDD
Industry STD TermPDIPPDIPSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY2525402500250040
CarrierTUBETUBETUBELARGE T&RLARGE T&RTUBE
Device MarkingCD74ACT109ECD74ACT109EACT109MACT109MACT109MACT109M
Width (mm)6.356.353.913.913.913.91
Length (mm)19.319.39.99.99.99.9
Thickness (mm)3.93.91.581.581.581.58
Pitch (mm)2.542.541.271.271.271.27
Max Height (mm)5.085.081.751.751.751.75
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsCD74ACT109E
CD74ACT109E
CD74ACT109EE4
CD74ACT109EE4
CD74ACT109M
CD74ACT109M
CD74ACT109M96
CD74ACT109M96
CD74ACT109M96E4
CD74ACT109M96E4
CD74ACT109ME4
CD74ACT109ME4
Bits222222
F @ Nom Voltage(Max), Mhz909090909090
ICC @ Nom Voltage(Max), mA0.040.040.040.040.040.04
Output Drive (IOL/IOH)(Max), mA-24/24-24/24-24/24-24/24-24/24-24/24
Package GroupPDIPPDIPSOICSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)16SOIC: 59 mm2: 6 x 9.9(SOIC)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyACTACTACTACTACTACT
VCC(Max), V5.55.55.55.55.55.5
VCC(Min), V4.54.54.54.54.54.5
Voltage(Nom), V555555
tpd @ Nom Voltage(Max), ns11.111.111.111.111.111.1

Öko-Plan

CD74ACT109ECD74ACT109EE4CD74ACT109MCD74ACT109M96CD74ACT109M96E4CD74ACT109ME4
RoHSCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYes

Anwendungshinweise

  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revision: A, Datei veröffentlicht: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop