Datasheet Texas Instruments ADS8341 — Datenblatt

HerstellerTexas Instruments
SerieADS8341
Datasheet Texas Instruments ADS8341

16-Bit-Analog-Digital-Wandler mit 4-Kanal-Abtastung und seriellem Ausgang

Datenblätter

ADS8341: 16-Bit, 4-Channel Serial Output Sampling Analog-To-Digital Converter datasheet
PDF, 1.4 Mb, Revision: D, Datei veröffentlicht: Apr 15, 2003
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Preise

Status

ADS8341EADS8341E/2K5ADS8341E/2K5G4ADS8341EBADS8341EB/2K5ADS8341EB/2K5G4ADS8341EBG4ADS8341EG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNo

Verpackung

ADS8341EADS8341E/2K5ADS8341E/2K5G4ADS8341EBADS8341EB/2K5ADS8341EB/2K5G4ADS8341EBG4ADS8341EG4
N12345678
Pin1616161616161616
Package TypeDBQDBQDBQDBQDBQDBQDBQDBQ
Industry STD TermSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY752500250075250025007575
CarrierTUBELARGE T&RLARGE T&RTUBELARGE T&RLARGE T&RTUBETUBE
Device Marking8341EADSADS8341EADSBADSADS
Width (mm)3.93.93.93.93.93.93.93.9
Length (mm)4.94.94.94.94.94.94.94.9
Thickness (mm)1.51.51.51.51.51.51.51.5
Pitch (mm).64.64.64.64.64.64.64.64
Max Height (mm)1.751.751.751.751.751.751.751.75
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsADS8341E
ADS8341E
ADS8341E/2K5
ADS8341E/2K5
ADS8341E/2K5G4
ADS8341E/2K5G4
ADS8341EB
ADS8341EB
ADS8341EB/2K5
ADS8341EB/2K5
ADS8341EB/2K5G4
ADS8341EB/2K5G4
ADS8341EBG4
ADS8341EBG4
ADS8341EG4
ADS8341EG4
# Input Channels44444444
Analog Voltage AVDD(Max), V5.255.255.255.255.255.255.255.25
Analog Voltage AVDD(Min), V2.72.72.72.72.72.72.72.7
ArchitectureSARSARSARSARSARSARSARSAR
Digital Supply(Max), V5.255.255.255.255.255.255.255.25
Digital Supply(Min), V2.72.72.72.72.72.72.72.7
INL(Max), +/-LSB66666666
Input Range(Max), V5.255.255.255.255.255.255.255.25
Input TypePseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-EndedPseudo-Differential,Single-Ended
Integrated FeaturesN/AN/AN/AN/AN/AN/AN/AN/A
InterfaceSerialSerialSerialSerialSerialSerialSerialSerial
Multi-Channel ConfigurationMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexed
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupSSOPSSOPSSOPSSOPSSOPSSOPSSOPSSOP
Package Size: mm2:W x L, PKG16SSOP: 19 mm2: 3.9 x 4.9(SSOP)16SSOP: 19 mm2: 3.9 x 4.9(SSOP)16SSOP: 19 mm2: 3.9 x 4.9(SSOP)16SSOP: 19 mm2: 3.9 x 4.9(SSOP)16SSOP: 19 mm2: 3.9 x 4.9(SSOP)16SSOP: 19 mm2: 3.9 x 4.9(SSOP)16SSOP: 19 mm2: 3.9 x 4.9(SSOP)16SSOP: 19 mm2: 3.9 x 4.9(SSOP)
Power Consumption(Typ), mW3.23.23.23.23.23.23.23.2
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExtExtExt
Resolution, Bits1616161616161616
SINAD, dBN/AN/AN/AN/AN/AN/AN/AN/A
SNR, dB8686868686868686
Sample Rate (max), SPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS100kSPS
Sample Rate(Max), MSPS0.10.10.10.10.10.10.10.1
THD(Typ), dB-90-90-90-90-90-90-90-90

Öko-Plan

ADS8341EADS8341E/2K5ADS8341E/2K5G4ADS8341EBADS8341EB/2K5ADS8341EB/2K5G4ADS8341EBG4ADS8341EG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

Anwendungshinweise

  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Datei veröffentlicht: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Modellreihe

Herstellerklassifikation

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)