Datasheet Texas Instruments ADS828 — Datenblatt

HerstellerTexas Instruments
SerieADS828
Datasheet Texas Instruments ADS828

10-Bit-75-MSPS-Analog-Digital-Wandler (ADC)

Datenblätter

ADS828: SpeedPlus? 10-Bit, 75MHz Sampling Analog-To-Digital Converter datasheet
PDF, 601 Kb, Revision: A, Datei veröffentlicht: Feb 23, 2001
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Preise

Status

ADS828EADS828E/1K
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo

Verpackung

ADS828EADS828E/1K
N12
Pin2828
Package TypeDBDB
Industry STD TermSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY501000
CarrierTUBELARGE T&R
Device MarkingADS828EADS828E
Width (mm)5.35.3
Length (mm)10.210.2
Thickness (mm)1.951.95
Pitch (mm).65.65
Max Height (mm)22
Mechanical DataHerunterladenHerunterladen

Parameter

Parameters / ModelsADS828E
ADS828E
ADS828E/1K
ADS828E/1K
# Input Channels11
Analog Input BW, MHz300300
ArchitecturePipelinePipeline
DNL(Max), +/-LSB11
DNL(Typ), +/-LSB0.40.4
ENOB, Bits9.39.3
INL(Max), +/-LSB33
INL(Typ), +/-LSB11
Input BufferNoNo
Input Range, Vp-p1,21,2
InterfaceParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Package GroupSSOPSSOP
Package Size: mm2:W x L, PKG28SSOP: 80 mm2: 7.8 x 10.2(SSOP)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)
Power Consumption(Typ), mW340340
RatingCatalogCatalog
Reference ModeExt,IntExt,Int
Resolution, Bits1010
SFDR, dB6868
SINAD, dB5757
SNR, dB5757
Sample Rate(Max), MSPS7575

Öko-Plan

ADS828EADS828E/1K
RoHSCompliantCompliant

Anwendungshinweise

  • ADS82x ADC with non-uniform sampling clock
    PDF, 234 Kb, Datei veröffentlicht: Feb 28, 2005
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Datei veröffentlicht: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Datei veröffentlicht: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, Datei veröffentlicht: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Datei veröffentlicht: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, Datei veröffentlicht: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, Datei veröffentlicht: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, Datei veröffentlicht: Apr 16, 2015

Modellreihe

Serie: ADS828 (2)

Herstellerklassifikation

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)