Datasheet Texas Instruments ADS5500 — Datenblatt

HerstellerTexas Instruments
SerieADS5500
Datasheet Texas Instruments ADS5500

14-Bit-Analog-Digital-Wandler (ADC) mit 125 MSPS

Datenblätter

14-Bit, 125MSPS Analog-to-Digital Converter datasheet
PDF, 1.8 Mb, Revision: F, Datei veröffentlicht: Feb 8, 2007
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Preise

Status

ADS5500IPAPADS5500IPAPR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNo

Verpackung

ADS5500IPAPADS5500IPAPR
N12
Pin6464
Package TypePAPPAP
Industry STD TermHTQFPHTQFP
JEDEC CodeS-PQFP-GS-PQFP-G
Package QTY1601000
CarrierJEDEC TRAY (10+1)LARGE T&R
Device MarkingADS5500IADS5500I
Width (mm)1010
Length (mm)1010
Thickness (mm)11
Pitch (mm).5.5
Max Height (mm)1.21.2
Mechanical DataHerunterladenHerunterladen

Parameter

Parameters / ModelsADS5500IPAP
ADS5500IPAP
ADS5500IPAPR
ADS5500IPAPR
# Input Channels11
Analog Input BW, MHz750750
ArchitecturePipelinePipeline
DNL(Max), +/-LSB0.750.75
DNL(Typ), +/-LSB0.750.75
ENOB, Bits11.311.3
INL(Max), +/-LSB2.52.5
INL(Typ), +/-LSB2.52.5
Input BufferNoNo
Input Range, Vp-p2.32.3
InterfaceParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Package GroupHTQFPHTQFP
Package Size: mm2:W x L, PKG64HTQFP: 144 mm2: 12 x 12(HTQFP)64HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW780780
RatingCatalogCatalog
Reference ModeIntInt
Resolution, Bits1414
SFDR, dB8383
SINAD, dB71.671.6
SNR, dB72.372.3
Sample Rate(Max), MSPS125125

Öko-Plan

ADS5500IPAPADS5500IPAPR
RoHSCompliantCompliant

Anwendungshinweise

  • 14-Bit, 125-MSPS ADS5500 Evaluation
    PDF, 738 Kb, Datei veröffentlicht: Jan 18, 2005
  • Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev
    PDF, 627 Kb, Datei veröffentlicht: Jun 25, 2004
    Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the
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  • Low-power, high-intercept interface to the ADS5424, 105-MSPS converter
    PDF, 478 Kb, Datei veröffentlicht: Oct 10, 2005
  • ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers
    PDF, 273 Kb, Datei veröffentlicht: Apr 22, 2004
    Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation
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    PDF, 2.0 Mb, Revision: A, Datei veröffentlicht: May 22, 2015
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    PDF, 1.2 Mb, Revision: A, Datei veröffentlicht: Jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Datei veröffentlicht: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, Datei veröffentlicht: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Datei veröffentlicht: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, Datei veröffentlicht: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, Datei veröffentlicht: May 18, 2015
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    PDF, 132 Kb, Revision: A, Datei veröffentlicht: Apr 16, 2015

Modellreihe

Serie: ADS5500 (2)

Herstellerklassifikation

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)