Datasheet Texas Instruments ADC08D1520QML-SP — Datenblatt

HerstellerTexas Instruments
SerieADC08D1520QML-SP
Datasheet Texas Instruments ADC08D1520QML-SP

Analog-Digital-Wandler (ADC) mit 8 Bit, Dual 1,5 GSPS oder Single 3,0 GSPS

Datenblätter

ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter datasheet
PDF, 1.2 Mb, Revision: O, Datei veröffentlicht: Mar 19, 2013
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Preise

Status

5962F0721401VZCADC08D1520WGFQVADC08D1520WGMPR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

Verpackung

5962F0721401VZCADC08D1520WGFQVADC08D1520WGMPR
N123
Pin128128128
Package TypeNBCNBCNBC
Industry STD TermCFPCFPCFP
JEDEC CodeS-CQFP-GS-CQFP-GS-CQFP-G
Package QTY121212
Device Marking5962F0721401VZC QADC08D1520WGFQVES
Width (mm)19.55819.55819.558
Length (mm)19.55819.55819.558
Thickness (mm)2.9972.9972.997
Pitch (mm).508.508.508
Max Height (mm)3.5563.5563.556
Mechanical DataHerunterladenHerunterladenHerunterladen

Parameter

Parameters / Models5962F0721401VZC
5962F0721401VZC
ADC08D1520WGFQV
ADC08D1520WGFQV
ADC08D1520WGMPR
ADC08D1520WGMPR
# Input Channels2,12,12,1
Analog Voltage AVDD(Max), V2.22.22.2
Analog Voltage AVDD(Min), V1.81.81.8
ArchitectureFolding InterpolatingFolding InterpolatingFolding Interpolating
ENOB, Bits7.47.47.4
INL(Max), +/-LSB666
INL(Typ), +/-LSB0.30.30.3
InterfaceParallel LVDSParallel LVDSParallel LVDS
Operating Temperature Range, C-55 to 125,25-55 to 125,25-55 to 125,25
Package GroupCFPCFPCFP
Package Size: mm2:W x L, PKGSee datasheet (CFP)See datasheet (CFP)See datasheet (CFP)
Power Consumption(Typ), mW200020002000
RatingSpaceSpaceSpace
Reference ModeIntIntInt
Resolution, Bits888
SFDR, dB55.555.555.5
SNR, dB474747
Sample Rate (max), SPS3GSPS3GSPS3GSPS

Öko-Plan

5962F0721401VZCADC08D1520WGFQVADC08D1520WGMPR
RoHSCompliantCompliantCompliant

Anwendungshinweise

  • AN-1558 Clocking High-Speed A/D Converters (Rev. B)
    PDF, 1.2 Mb, Revision: B, Datei veröffentlicht: May 1, 2013
    Extremely high-speed ADCs (>1 GSPS) demand a low-jitter sample clock in order to preserve signal-tonoiseratio (SNR). These 8- and 10-bit converters have best-case noise floors set by quantization noise.For an N-bit ADC sampling a full-scale sinusoid, the well known expression for SNR (in dB) is: SNR =6.02N + 1.76. This sets the best case noise floor for an 8-bit ADC at в€’49.9 dBc. The noise f

Modellreihe

Herstellerklassifikation

  • Semiconductors> Space & High Reliability> Data Converter> Analog to Digital Converters