Datasheet Texas Instruments CLVTH16244AQDGGREP — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH16244A-EP
ArtikelnummerCLVTH16244AQDGGREP
Datasheet Texas Instruments CLVTH16244AQDGGREP

Erweitertes Produkt 3.3-V Abt 16-Bit-Puffer / Treiber mit 3-Zustands-Ausgängen 48-TSSOP -40 bis 125

Datenblätter

SN74LVTH16244A-EP datasheet
PDF, 707 Kb, Revision: F, Datei veröffentlicht: Apr 23, 2007
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin48
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLH16244AEP
Width (mm)6.1
Length (mm)12.5
Thickness (mm)1.15
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataHerunterladen

Parameter

Bits16
Input TypeTTL/CMOS
Operating Temperature Range-40 to 125,-40 to 85,-55 to 125 C
Output TypeLVTTL
Package GroupTSSOP
Package Size: mm2:W x L48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG
RatingHiRel Enhanced Product
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
Voltage(Nom)3.3 V

Öko-Plan

RoHSCompliant

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, Revision: A, Datei veröffentlicht: Aug 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, Datei veröffentlicht: May 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, Datei veröffentlicht: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Modellreihe

Herstellerklassifikation

  • Semiconductors > Space & High Reliability > Logic Products > Buffers/Drivers/Transceivers > Buffer Drivers