Datasheet Texas Instruments ADS8363SRHBT — Datenblatt

16-Bit-, 1-MSPS-, 4x2 / 2x2-SAR-ADC 32-VQFN -40 bis 125 mit gleichzeitiger Abtastung

Datenblätter

PDF, 1.4 Mb, Revision: D, Datei veröffentlicht: Sep 2, 2017

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Using the Sequencer and Pseudo-Differential Features of the ADS8363
PDF, 161 Kb, Datei veröffentlicht: May 21, 2014
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Interfacing to the ADS8363 Pseudo-Differential Operating Mode
PDF, 548 Kb, Datei veröffentlicht: Aug 4, 2014
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Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
PDF, 227 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
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Determining Minimum Acquisition Times for SAR ADCs, part 2
PDF, 215 Kb, Datei veröffentlicht: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Serie: ADS8363 (2)

Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)