Datasheet Texas Instruments SN74LVT574DW — Datenblatt
| Hersteller | Texas Instruments |
| Serie | SN74LVT574 |
| Artikelnummer | SN74LVT574DW |
3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops mit 3-State-Ausgängen 20-SOIC -40 bis 85
Datenblätter
3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs datasheet
PDF, 837 Kb, Revision: D, Datei veröffentlicht: Jul 1, 1995
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Status
| Lifecycle Status | NRND (Not recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 20 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | LVT574 |
| Width (mm) | 7.5 |
| Length (mm) | 12.8 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | Herunterladen |
Ersatz
| Replacement | SN74LVTH574DW |
| Replacement Code | Q |
Öko-Plan
| RoHS | Compliant |
Anwendungshinweise
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Modellreihe
Serie: SN74LVT574 (7)
Herstellerklassifikation
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop