Datasheet Texas Instruments TMS320C6671ACYP — Datenblatt
| Hersteller | Texas Instruments |
| Serie | TMS320C6671 |
| Artikelnummer | TMS320C6671ACYP |
Digitaler Fest- und Gleitkomma-Signalprozessor 841-FCBGA 0 bis 85
Datenblätter
TMS320C6671 Fixed and Floating-Point Digital Signal Processor datasheet
PDF, 2.1 Mb, Revision: E, Datei veröffentlicht: May 7, 2014
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Preise
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Verpackung
| Pin | 841 | 841 |
| Package Type | CYP | CYP |
| Package QTY | 44 | 44 |
| Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
| Device Marking | TMS320C6671CYP | @2010 TI |
| Width (mm) | 24 | 24 |
| Length (mm) | 24 | 24 |
| Thickness (mm) | 2.82 | 2.82 |
| Mechanical Data | Herunterladen | Herunterladen |
Parameter
| Applications | Communications and Telecom |
| DRAM | DDR3 |
| DSP | 1 C66x |
| DSP MHz | 1000,1250 Max. |
| EMAC | 2-Port 1Gb Switch |
| GFLOPS | 16,20 |
| On-Chip L2 Cache | 512 KB |
| Operating Temperature Range | -40 to 100,0 to 85 C |
| Other On-Chip Memory | 4096 KB |
| PCI/PCIe | 2 PCIe Gen2 |
| Package Size: mm2:W x L | See datasheet (FCBGA) PKG |
| Rating | Catalog |
| Serial I/O | I2C,RapidIO,SPI,TSIP,UART |
| Serial RapidIO | 1 (four lanes) |
| Total On-Chip Memory | 4800 KB |
Öko-Plan
| RoHS | Compliant |
Design Kits und Evaluierungsmodule
- JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - Development Kits: HL5CABLE
Hyperlink Cable
Lifecycle Status: Active (Recommended for new designs) - Development Kits: TMDSEVM6678
TMS320C6678 Evaluation Modules
Lifecycle Status: Active (Recommended for new designs) - Daughter Cards: TMDXEVMPCI
AMC to PCIe Adapter Card
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs)
Anwendungshinweise
- TI Keystone DSP Hyperlink SerDes IBIS-AMI ModelsPDF, 3.2 Mb, Datei veröffentlicht: Oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface. - TI Keystone DSP PCIe SerDes IBIS-AMI ModelsPDF, 4.8 Mb, Datei veröffentlicht: Oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface. - SerDes Implementation Guidelines for KeyStone I DevicesPDF, 590 Kb, Datei veröffentlicht: Oct 31, 2012
The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge - KeyStone I DDR3 Initialization (Rev. E)PDF, 114 Kb, Revision: E, Datei veröffentlicht: Oct 28, 2016
The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP - TMS320C66x DSP Generation of Devices (Rev. A)PDF, 245 Kb, Revision: A, Datei veröffentlicht: Apr 25, 2011
- Hardware Design Guide for KeyStone Devices (Rev. C)PDF, 1.7 Mb, Revision: C, Datei veröffentlicht: Sep 15, 2013
- SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, Datei veröffentlicht: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices. - PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, Datei veröffentlicht: Dec 13, 2011
- Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, Datei veröffentlicht: Nov 9, 2010
- The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM - Optimizing Loops on the C66x DSPPDF, 585 Kb, Datei veröffentlicht: Nov 9, 2010
- DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, Revision: B, Datei veröffentlicht: Jun 5, 2014
- Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, Revision: B, Datei veröffentlicht: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
Modellreihe
Serie: TMS320C6671 (4)
- TMS320C6671ACYP TMS320C6671ACYP25 TMS320C6671ACYPA TMS320C6671ACYPA25
Herstellerklassifikation
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP > C66x DSP