Datasheet Texas Instruments TPS40077PWPG4 — Datenblatt

TPS40077
www.ti.com . SLUS714D – JANUARY 2007 – REVISED APRIL 2009 HIGH-EFFICIENCY, MIDRANGE-INPUT, SYNCHRONOUS
BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD
FEATURES CONTENTS 1 Operation Over 4.5-V to 28-V Input Range Programmable, Fixed-Frequency, up to 1-MHz,
Voltage-Mode Controller Predictive Gate Driveв„ў Anti-Cross-Conduction
Circuitry 10 V 7 8 VDD = 4.5 V, IOUT = 25 mA 4 4.3 9 V ERROR AMPLIFIER
TJ = 25°C 0.698 0.7 0.704 0°C ≤ TJ ≤ 85°C 0.69 0.7 0.707 –40°C ≤ TJ ≤ 85°C 0.69 0.7 0.715 VFB Feedback regulation voltage total variation VSS Soft-start offset from VSS (1) GBW Gain bandwidth (1) AVOL Open-loop gain 50 ISRC Output source current 2.5 4.5 ISINK Output sink current 2.5 6 IBIAS Input bias current (1) 4 Offset from VSS to error amplifier
5 VFB = 0.7 V –250 V 1 V 10 MHz
dB
mA
0 nA Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s) :TPS40077 TPS40077
www.ti.com . SLUS714D – JANUARY 2007 – REVISED APRIL 2009 ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 80 105 125 µA –75 –50 –30 mV 135 225 ns SHORT-CIRCUIT CURRENT PROTECTION
IILIM Current sink into current limit VILIM(ofst) Current limit offset voltage (VSW – VILIM) VILIM = 11.5 V, VVDD = 12 V tHSC Minimum HDRV pulse duration During short circuit Propagation delay to output (2) 50 ns 50 ns tBLANK Blanking time (2) tOFF Off time during a fault (SS cycle times) 7 Cycles VSW Switching level to end precondition
(VVDD – VSW) (2) 2 V tPC Precondition time (2) VILIM Current limit precondition voltage threshold (2) 100 ns 6.8 V 36 ns 48 ns 72 ns 96 ns 24 ns 48 ns CLDRV = 2200 pF, VVDD = 4.5 V,
0.2 V ≤ VSS ≤ 4 V 48 ns IHDRV = –0.01 A 0.7 1 IHDRV = –0.1 A 0.95 1.3 IHDRV = 0.01A 0.06 0.1 IHDRV = 0.1 A 0.65 1 OUTPUT DRIVERS
tHFALL High-side driver fall time (HDRV – SW) (2)
(2) tHRISE High-side driver rise time (HDRV – SW) tHFALL High-side driver fall time (HDRV – SW) (2) tHRISE High-side driver rise time (HDRV – SW) (2) CHDRV = 2200 pF
CHDRV = 2200 pF, VVDD = 4.5 V,
0.2 V ≤ VSS ≤ 4 V (2) tLFALL Low-side driver fall time tLRISE Low-side driver rise time (2) tLFALL Low-side driver fall time (2) CLDRV = 2200 pF (2) tLRISE Low-side driver rise time VOH High-level output voltage, HDRV
(VBOOST – VHDRV) VOL Low-level output voltage, HDRV (VHDRV – VSW) VOH High-level output voltag …