Datasheet Texas Instruments ADS7263SRHBT — Datenblatt

HerstellerTexas Instruments
SerieADS7263
ArtikelnummerADS7263SRHBT
Datasheet Texas Instruments ADS7263SRHBT

14-Bit 1MSPS 4x2 / 2x2 Simultane Abtastung SAR ADC 32-VQFN -40 bis 125

Datenblätter

ADSxxx3 Dual, 1-MSPS, 16-, 14-, and 12-Bit, 4Г—2 or 2Г—2 Channel, Simultaneous Sampling Analog-to-Digital Converter datasheet
PDF, 1.4 Mb, Revision: D, Datei veröffentlicht: Sep 2, 2017
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

Verpackung

Pin3232
Package TypeRHBRHB
Industry STD TermVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-N
Package QTY250250
CarrierSMALL T&RSMALL T&R
Device Marking7263ADS
Width (mm)55
Length (mm)55
Thickness (mm).9.9
Pitch (mm).5.5
Max Height (mm)11
Mechanical DataHerunterladenHerunterladen

Parameter

# Input Channels4
Analog Voltage AVDD(Max)5.5 V
Analog Voltage AVDD(Min)2.7 V
ArchitectureSAR
Digital Supply(Max)5.5 V
Digital Supply(Min)2.3 V
INL(Max)2 +/-LSB
Input Range(Max)5.5 V
Input TypeDifferential,Pseudo-Differential
Integrated FeaturesN/A
InterfaceSPI
Multi-Channel ConfigurationMultiplexed,Simultaneous Sampling
Operating Temperature Range-40 to 125 C
Package GroupVQFN
Package Size: mm2:W x L32VQFN: 25 mm2: 5 x 5(VQFN) PKG
Power Consumption(Typ)47.2 mW
RatingCatalog
Reference ModeExt,Int
Resolution14 Bits
SINAD84 dB
SNR85 dB
Sample Rate (max)1MSPS SPS
Sample Rate(Max)1 MSPS
THD(Typ)-92 dB

Öko-Plan

RoHSCompliant

Design Kits und Evaluierungsmodule

  • Evaluation Modules & Boards: ADS8363EVM
    ADS8363 Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

Anwendungshinweise

  • Using the Sequencer and Pseudo-Differential Features of the ADS8363
    PDF, 161 Kb, Datei veröffentlicht: May 21, 2014
  • Interfacing to the ADS8363 Pseudo-Differential Operating Mode
    PDF, 548 Kb, Datei veröffentlicht: Aug 4, 2014
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Datei veröffentlicht: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, Datei veröffentlicht: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, Datei veröffentlicht: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, Datei veröffentlicht: Apr 16, 2015

Modellreihe

Serie: ADS7263 (2)

Herstellerklassifikation

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)