Datasheet Texas Instruments DAC5686IPZPG4 — Datenblatt

HerstellerTexas Instruments
SerieDAC5686
ArtikelnummerDAC5686IPZPG4
Datasheet Texas Instruments DAC5686IPZPG4

Zweikanaliger 16-Bit-, 500-MSPS-, 1x-16x-Interpolations-Digital-Analog-Wandler (DAC) 100-HTQFP -40 bis 85

Datenblätter

16-Bit 500 MSPS 2x-16x Interpolating Dual-Channel DAC datasheet
PDF, 861 Kb, Revision: F, Datei veröffentlicht: Jun 3, 2009
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin100
Package TypePZP
Industry STD TermHTQFP
JEDEC CodeS-PQFP-G
Package QTY90
CarrierEIAJ TRAY (10+1)
Device MarkingDAC5686IPZP
Width (mm)14
Length (mm)14
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataHerunterladen

Parameter

ArchitectureCurrent Sink
DAC Channels2
InterfaceParallel CMOS
Interpolation1x,2x,4x,8x,16x
Operating Temperature Range-40 to 85 C
Package GroupHTQFP
Package Size: mm2:W x L100HTQFP: 256 mm2: 16 x 16(HTQFP) PKG
Power Consumption(Typ)445 mW
RatingCatalog
Resolution16 Bits
SFDR72 dB
Sample / Update Rate500 MSPS

Öko-Plan

RoHSCompliant

Design Kits und Evaluierungsmodule

  • Evaluation Modules & Boards: TSW3100EVM
    TSW3100 Pattern Generator Module
    Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

Anwendungshinweise

  • DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A)
    PDF, 686 Kb, Revision: A, Datei veröffentlicht: Jul 21, 2005
    DAC5686/DAC5687 Application NOte Clock Generation Using PLL & External Clock Modes
  • Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
    PDF, 319 Kb, Datei veröffentlicht: Jul 14, 2009
  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, Datei veröffentlicht: Nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
  • Q3 2009 Issue Analog Applications Journal
    PDF, 2.1 Mb, Datei veröffentlicht: Jul 14, 2009
  • High Speed Digital-to-Analog Converters Basics (Rev. A)
    PDF, 829 Kb, Revision: A, Datei veröffentlicht: Oct 23, 2012
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Datei veröffentlicht: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Modellreihe

Serie: DAC5686 (2)

Herstellerklassifikation

  • Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)