Datasheet Texas Instruments SN74LVTH125DBR — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH125
ArtikelnummerSN74LVTH125DBR
Datasheet Texas Instruments SN74LVTH125DBR

3,3-V-ABT-Vierfachbuspuffer mit 3-Zustands-Ausgängen 14-SSOP -40 bis 85

Datenblätter

SN54LVTH125, SN74LVTH125 datasheet
PDF, 1.1 Mb, Revision: I, Datei veröffentlicht: Oct 13, 2003
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin14
Package TypeDB
Industry STD TermSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLXH125
Width (mm)5.3
Length (mm)6.2
Thickness (mm)1.95
Pitch (mm).65
Max Height (mm)2
Mechanical DataHerunterladen

Parameter

Bits4
F @ Nom Voltage(Max)160 Mhz
ICC @ Nom Voltage(Max)0.007 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)-32/64 mA
Package GroupSSOP
Package Size: mm2:W x L14SSOP: 48 mm2: 7.8 x 6.2(SSOP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
Voltage(Nom)3.3 V
tpd @ Nom Voltage(Max)3.5 ns

Öko-Plan

RoHSCompliant

Anwendungshinweise

  • Simultaneous-Switching Performance of TI Logic Devices (Rev. B)
    PDF, 378 Kb, Revision: B, Datei veröffentlicht: Feb 23, 2005
    Simultaneous-switching noise can generate and propagate glitches in electronic systems. Therefore, system designers are faced with challenges to minimize simultaneous-switching noise, while increasing switching speed and improving signal quality. This report presents the performance of different TI logic devices under various simultaneous-switching conditions. Factors such as the number of bits sw
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors > Logic > Buffer/Driver/Transceiver > Non-Inverting Buffer/Driver