Datasheet Texas Instruments ADS8413IBRGZRG4 — Datenblatt

HerstellerTexas Instruments
SerieADS8413
ArtikelnummerADS8413IBRGZRG4
Datasheet Texas Instruments ADS8413IBRGZRG4

16-Bit, unipolarer Diff-Eingang, 2MSPS-Abtastrate, 4,75 V bis 5,25 V ADC mit serieller LVDS-Schnittstelle 48-VQFN -40 bis 85

Datenblätter

16-Bit, 2-MSPS, LVDS Serial Interface, SAR ADC datasheet
PDF, 1.6 Mb, Datei veröffentlicht: Oct 6, 2005
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Preise

Status

Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNo

Verpackung

Pin48
Package TypeRGZ
Industry STD TermVQFN
JEDEC CodeS-PQFP-N
Width (mm)7
Length (mm)7
Thickness (mm).9
Pitch (mm).5
Max Height (mm)1
Mechanical DataHerunterladen

Parameter

# Input Channels1
Analog Voltage AVDD(Max)(V)5.25
Analog Voltage AVDD(Min)(V)4.75
Approx. Price (US$)21.35 | 1ku
ArchitectureSAR
Digital Supply(Max)(V)5.25
Digital Supply(Min)(V)2.7
INL(Max)(+/-LSB)2
Input Range(Max)(V)4.096
Input TypeDifferential
Integrated FeaturesDaisy-Chainable
Oscillator
InterfaceParallel
Multi-Channel ConfigurationN/A
Operating Temperature Range(C)-40 to 85
Package GroupVQFN
Package Size: mm2:W x L (PKG)48VQFN: 49 mm2: 7 x 7(VQFN)
Power Consumption(Typ)(mW)155
RatingCatalog
Reference ModeExt
Int
Resolution(Bits)16
SINAD(dB)92
SNR(dB)92
Sample Rate (max)(SPS)2MSPS
THD(Typ)(dB)-107

Öko-Plan

RoHSNot Compliant
Pb FreeNo

Anwendungshinweise

  • Connecting ADS8410/13 With Long Cable
    PDF, 773 Kb, Datei veröffentlicht: Dec 2, 2005
    Many applications require that the analog-to-digital converter (ADC) be located near the field sensor; however, the digital processing often occurs at a distance. Therefore, the input and output signals need to travel through a long cable from the field sensor to the site where digital processing occurs. This application report is a guide for using a 1-meter cable, the Samtec EQCD Series high data
  • Using ADS8410/13 in Daisy Chain Mode
    PDF, 3.2 Mb, Datei veröffentlicht: May 22, 2006
    Many applications require multiple analog-to-digital converters (ADC) in a system. Daisy chaining multiple ADCs enables the use of a single data receiver or a small FPGA. It offers easy and minimal digital routing. This application report describes how multiple ADCs (ADS8410/13) work in a daisy-chain mode. The device offers a high-speed (200 Mbps) LVDS serial interface. This application report als
  • Using ADS8410/13 in Cascade Mode
    PDF, 2.9 Mb, Datei veröffentlicht: Jun 8, 2006
    Many applications require multiple analog-to-digital converters (ADC) in a system. Cascading multiple ADCs enables the use of a single data receiver or a small FPGA. This offers lower power consumption and independent ADC usage. This application report describes how multiple ADCs (ADS8410/13) work in a cascade mode. The ADS8410/13 integrated circuit offers a high-speed (200 Mbps) LVDS serial inter
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Datei veröffentlicht: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Modellreihe

Herstellerklassifikation

  • Semiconductors > Data Converters > Analog to Digital Converter > Precision ADC (<=10MSPS)